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DP83867CS 数据表(PDF) 75 Page - Texas Instruments

部件名 DP83867CS
功能描述  DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
PDF  129 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

DP83867CS 数据表(HTML) 75 Page - Texas Instruments

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7.6.29 Fast Link Drop Configuration Register (FLD_CFG)
Table 7-39. Fast Link Drop Configuration Register (FLD_CFG), Address 0x002D
BIT
BIT NAME
DEFAULT
DESCRIPTION
15
FORCE_DROP
0, RW
Force Drop Link
Forces the link partner to drop the link when no signal is received.
1 = Drops link
0 = Normal operation
14
FLD_EN
0, RW
1000BASE-T Fast Link Drop:
This bit must be set to 0 during the link up process. After the link is
established set this bit to 1 to enable FLD.
1 = Enable FLD
0 = Normal operation
13
RESERVED
0, RO
RESERVED
12:8
FLD_STS
0, RO, LH
Fast Link Drop Status:
Status Registers that latch high each time a given Fast Link Down
mode is activated and causes a link drop (assuming this criterion
was enabled):
Bit 12: Descrambler Loss Sync
Bit 11: RX Errors
Bit 10: MLT3 Errors
Bit 9: SNR level
Bit 8: Signal/Energy Lost
7:5
RESERVED
0, RO
RESERVED
4:0
FLD_SRC_CFG
0, RW
Fast Link Drop Source Configuration:
The following FLD sources can be configured independently:
Bit 4: Descrambler Loss Sync
Bit 3: RX Errors
Bit 2: MLT3 Errors
Bit 1: SNR level
Bit 0: Signal/Energy Lost
www.ti.com
DP83867CS, DP83867IS, DP83867E
SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: DP83867CS DP83867IS DP83867E



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