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DP83867CS 数据表(PDF) 40 Page - Texas Instruments |
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DP83867CS 数据表(HTML) 40 Page - Texas Instruments |
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40 / 129 page ![]() Table 7-6. 4-Level Strap Pins (continued) PIN NAME 48VQFN PIN # DEFAULT STRAP FUNCTION LED_1 46 [00] MODE ANEG_SEL RGMII Clock Skew TX[2] 1 0 0 2 0 1 3 1 0 4 1 1 LED_0 47 [00] MODE Mirror Enable SGMII Enable 1 0 0 2 0 1 3 1 0 4 1 1 (1) Strap modes 1 and 2 are not applicable for RX_CTRL. The RX_CTRL strap must be configured for strap mode 3 or strap mode 4. If the RX_CTRL pin cannot be strapped to mode 3 or mode 4, bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. Autoneg Disable can always be set to 0 when using gigabit Ethernet. (2) Only Mode 1 and 3 are valid for GPIO_0. Mode 2 and 4 are not applicable and can not be used. Note RX_D1 is not a strap input, but this pin must be populated with the same strap resistors chosen for RX_D0. RX_D0 and RX_D1 form an SGMII differential pair. The dummy straps on RX_D1 are required to provide a balanced load for this SGMII differential pair. Note RX_D3 is not a strap input, but this pin must be populated with the same strap resistors chosen for RX_D2. RX_D2 and RX_D3 form an SGMII differential pair. The dummy straps on RX_D3 are required to provide a balanced load for this SGMII differential pair. Table 7-7. Auto-Negotiation Select Strap Details MODE ANEG_SEL REMARKS 10/100/1000 0 advertise ability of 10/100/1000 100/1000 1 advertise ability of 100/1000 only Table 7-8. RGMII Transmit Clock Skew Details MODE RGMII CLOCK SKEW TX[2] RGMII CLOCK SKEW TX[1] RGMII CLOCK SKEW TX[0] RGMII TX CLOCK SKEW 1 0 0 0 2.0ns 2 0 0 1 1.5ns 3 0 1 0 1.0ns 4 0 1 1 0.5ns 5 1 0 0 0ns 6 1 0 1 3.5ns 7 1 1 0 3.0ns 8 1 1 1 2.5ns DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 www.ti.com 40 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E |
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