DP83867CS datasheet(36/129 Pages) TI2

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• Link fails or is dropped by setting bit 7 of register 0x0009 (CFG1). The results of the TDR run after the link

fails are saved in the TDR registers.

Software reads these registers at any time to apply post processing on the TDR results. This mode is designed

for cases when the link dropped due to cable disconnections; after link failure, for instance, the line is quiet to

allow a proper function of the TDR.

7.4.6.2 Energy Detect

The energy-detector module provides signal-strength indication in various scenarios. Because the detection is

based on an IIR filter, this robust energy detector has excellent reaction time and reliability. The filter output

is compared to predefined thresholds to decide the presence or absence of an incoming signal. The energy

detector also implements hysteresis to avoid jittering in signal-detect indication. Additionally, the PHY has

fully-programmable thresholds and listening-time periods, enabling shortening of the reaction time if required.

7.4.6.3 Fast Link Detect

Several advanced modes are available for fast link establishment. Unlike the Auto-Negotiation and Auto-MDIX

mechanisms defined by the IEEE 802.3 specification, these modes are specific to the DP83867. Take care when

implementing these modes. For best operation, TI recommends implementing these modes with a DP83867 on

both ends of the link.

These advanced link and crossover modes depend on the speed selected for the link. Some modes are intended

for use in 1000Base-T operation. Others are intended for use in 100Base-TX operation.

Fast Link Detect functionality can be configured using the Configuration Register 3 (CFG3), address 0x001E.

7.4.6.4 Speed Optimization

Speed optimization, also known as link downshift, enables fallback to 100M operation after multiple consecutive

failed attempts at Gigabit link establishment. Such a case can occur if cabling with only four wires (two twisted

pairs) are connected instead of the standard cabling with eight wires (four twisted pairs).

The number of failed link attempts before falling back to 100M operation is configurable. By default, four failed

link attempts are required before falling back to 100M.

In enhanced mode, fallback to 100M can occur after one failed link attempt if energy is not detected on the C

and D channels. Speed optimization also supports fallback to 10M if link establishment fails in Gigabit and in

100M mode.

Speed optimization can be enabled through register configuration.

7.4.6.5 Mirror Mode

In some multiport applications, RJ-45 ports can be mirrored relative to one another. This mirroring can require

crossing board traces. The DP83867 can resolve this issue by implementing mirroring of the ports inside the

device.

In 10/100 operation, the mapping of the port mirroring is:

MDI MODE

MIRROR PORT CONFIGURATION

MDI

A → D

B → C

MDIX

A → D

B → C

In Gigabit operation, the mapping of the port mirroring is:

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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