MPC8309CVMADFC datasheet(32/81 Pages) NXP

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

HDLC

10.1

HDLC DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8309 HDLC protocol.

10.2

HDLC AC Timing Specifications

The following table provides the input and output AC timing specifications for HDLC protocol.

The following figure provides the AC test load.

Figure 22. AC Test Load

Table 30. HDLC DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

VOH

IOH = –2.0 mA

2.4

—

Output low voltage

VOL

IOL = 3.2 mA

—

0.5

Input high voltage

VIH

—2.0

OVDD +0.3

Input low voltage

VIL

—–0.3

0.8

Input current

IIN

0 V

 VIN OVDD

—

±5

A

Table 31. HDLC AC Timing Specifications1

Characteristic

Symbol2

Min

Max

Unit

Outputs—Internal clock delay

tHIKHOV

Outputs—External clock delay

tHEKHOV

Outputs—Internal clock high impedance

tHIKHOX

05.5

Outputs—External clock high impedance

tHEKHOX

Inputs—Internal clock input setup time

tHIIVKH

9—

Inputs—External clock input setup time

tHEIVKH

4—

Inputs—Internal clock input hold time

tHIIXKH

0—

Inputs—External clock input hold time

tHEIXKH

1—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs

internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

Output

Z0 = 50 

OVDD/2

RL = 50 

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