MPC8309CVMADFC datasheet(4/81 Pages) NXP

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Overview

For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference

Manual with Protocol Interworking.

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DDR SDRAM memory controller

— Programmable timing supporting DDR2 SDRAM

— Integrated SDRAM clock generation

— Supports 8-bit ECC

— 16/32-bit data interface, up to 333-MHz data rate

— 14 address lines

— The following SDRAM configurations are supported:

– Up to two physical banks (chip selects), 512-Mbyte addressable space for 32 bit data

interface

– 64-Mbit to 2-Gbit devices with x8/x16/x32 data ports (no direct x4 support)

— One 16-bit device or two 8-bit devices on a 16-bit bus, or two 16-bit devices or four 8-bit

devices on a 32-bit bus Support for up to 16 simultaneous open pages for DDR2

— Two clock pair to support up to 4 DRAM devices

— Supports auto refresh

— On-the-fly power management using CKE

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Enhanced local bus controller (eLBC)

— Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz

— Eight chip selects supporting eight external slaves

– Four chip selects dedicated

– Four chip selects offered as multiplexed option

— Supports boot from parallel NOR Flash and parallel NAND Flash

— Supports programmable clock ratio dividers

— Up to eight-beat burst transfers

— 16- and 8-bit ports, separate LWE for each 8 bit

— Three protocol engines available on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

– NAND Flash control machine (FCM)

— Variable memory block sizes for FCM, GPCM, and UPM mode

— Default boot ROM chip select with configurable bus width (8 or 16)

— Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC

slave devices

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Integrated programmable interrupt controller (IPIC)

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for external and internal discrete interrupt sources

— Programmable highest priority request

MPC8309CVMADFC 数据表(PDF) 4 Page - NXP Semiconductors

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