MPC8309CVMADFC datasheet(12/81 Pages) NXP

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Clock Input Timing

The following table shows the estimated typical I/O power dissipation for the device.

Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8309.

NOTE

The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This

should be enforced especially on clock signals. Rise time refers to signal

transitions from 10% to 90% of OVDD; fall time refers to transitions from

90% to 10% of OVDD.

4.1

DC Electrical Characteristics

The following table provides the clock input (SYS_CLK_IN/PCI_SYNC_IN) DC specifications for the

MPC8309. These specifications are also applicable for QE_CLK_IN.

Table 6. Typical I/O Power Dissipation

Interface

Parameter

GVDD

(1.8 V)

OVDD

(3.3 V)

Unit

Comments

DDR I/O

65% utilization

1.8 V

Rs = 20 

Rt = 50 

1 pair of clocks

266 MHz, 1

 16 bits

0.149

—W

—

Local bus I/O load = 25 pF

1 pair of clocks

66 MHz, 26 bits

—0.415

QUICC Engine block and other I/Os

TDM serial, HDLC/TRAN serial,

DUART, MII, RMII, Ethernet

management, USB, PCI, SPI, Timer

output, FlexCAN, eSDHC

Note:

1. Typical I/O power is based on a nominal voltage of VDD = 3.3V, ambient temperature, and the core running a Dhrystone

benchmark application. The measurements were taken on the evaluation board using WC process silicon.

Table 7. SYS_CLK_IN DC Electrical Characteristics

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

—

VIH

2.4

OVDD +0.3

Input low voltage

—

VIL

–0.3

0.4

SYS_CLK_IN input current

0 V

 VIN  OVDD

IIN

—±5

A

SYS_CLK_IN input current

0 V

 VIN  0.5 V or

OVDD – 0.5 V  VIN OVDD

IIN

—±5

A

SYS_CLK_IN input current

0.5 V

 VIN  OVDD – 0.5 V

IIN

—±50

A

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