MPC8309CVMADFC datasheet(69/81 Pages) NXP

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Clocking

23.5

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). The following table shows the encodings for RCWL[COREPLL]. COREPLL

values not listed, and should be considered reserved.

Table 59. CSB Frequency Options

SPMF

csb_clk : sys_clk_in Ratio

PCI_SYNC_IN(MHz)

33.33

66.67

csb_clk Frequency (MHz)

0010

2:1

133

0011

3:1

0100

4:1

133

0101

5:1

125

167

0110

6:1

Table 60. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider

0-1

2-5

0000

PLL bypassed

(PLL off, csb_clk clocks core directly)

PLL bypassed

(PLL off, csb_clk clocks core directly)

0001

1:1

2

0001

1:1

4

0001

1:1

8

0001

1:1

8

0001

1.5:1

 2

0001

1.5:1

 4

0001

1.5:1

 8

0001

1.5:1

 8

0010

2:1

 2

0010

2:1

 4

0010

2:1

 8

0010

2:1

 8

0010

2.5:1

 2

0010

2.5:1

 4

0010

2.5:1

 8

0010

2.5:1

 8

0011

3:1

 2

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