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MPC8309CVMADFC 数据表(PDF) 33 Page - NXP Semiconductors |
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MPC8309CVMADFC 数据表(HTML) 33 Page - NXP Semiconductors |
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33 / 81 page ![]() MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 33 PCI Figure 23 and Figure 24 represent the AC timing from Table 31. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. The following figure shows the timing with external clock. Figure 23. AC Timing (External Clock) Diagram The following figure shows the timing with internal clock. Figure 24. AC Timing (Internal Clock) Diagram 11 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8309. 11.1 PCI DC Electrical Characteristics Table 32 provides the DC electrical characteristics for the PCI interface of the MPC8309. Table 32. PCI DC Electrical Characteristics1,2 Parameter Symbol Test Condition Min Max Unit High-level input voltage VIH VOUT VOH (min) or 2 OVDD + 0.3 V Low-level input voltage VIL VOUT VOL (max) –0.3 0.8 V High-level output voltage VOH OVDD = min, IOH = –100 A OVDD – 0.2 — V Serial CLK (Input) tHEIXKH tHEIVKH tHEKHOV Input Signals: (See Note) Output Signals: (See Note) Note: The clock edge is selectable. tHEKHOX Serial CLK (Output) tHIIXKH tHIKHOV Input Signals: (See Note) Output Signals: (See Note) tHIIVKH tHIKHOX Note: The clock edge is selectable. |
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