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ST10 数据表(PDF) 9 Page - STMicroelectronics |
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ST10 数据表(HTML) 9 Page - STMicroelectronics |
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9 / 58 page ![]() ST10F163 9/58 III - FUNCTIONAL DESCRIPTION The architecture of the ST10F163 combines the advantages of both RISC and CISC processors and an advanced peripheral subsystem. The fol- lowing block diagram gives an overview of the dif- ferent on-chip components and of the advanced, high bandwidth internal bus structure. Figure 3 : Block diagram OSC. Port 6 Port 5 Port 3 Port 2 Ext. Bus Con- troller SSP BRG GPT1 T2 T3 T4 GPT2 T5 T6 ASC (usart) BRG Internal FLASH Memory CPU-Core Internal RAM Watchdog Interrupt Controller 16 16 8 8 8 15 6 32 16 PEC 16 16 16 16 PLL |
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