ST10 datasheet(19/58 Pages) STMICROELECTRONICS

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ST10F163

19/58

The ST10F163 provides an excellent mechanism

to identify and to process exceptions or error con-

ditions that arise during run-time, called‘Hardware

Traps’.

Hardware

traps

cause

immediate

non-maskable system reaction which is similar to

a standard interrupt service (branching to a dedi-

cated vector table location). The occurrence of a

hardware trap is additionally signified by an indi-

vidual bit in the trap flag register (TFR). Except

when another higher prioritized trap service is in

progress, a hardware trap will interrupt any actual

program execution. In turn, hardware trap ser-

vices can normally not be interrupted by standard

or PEC interrupts.

Table 7 shows all of the possible exceptions or

error conditions that can arise during run time.

SSP Interrupt

XP1IR

XP1IE

XP1INT

00’0104h

41h

PLL Unlock / OWD

XP3IR

XP3IE

XP3INT

00’010Ch

43h

Table 6 : List of possible interrupt sources, flags, vector and trap numbers (continued)

Source of Interrupt or PEC

Service Request

Request

Flag

Enable

Flag

Interrupt

Vector

Location

Trap

Number

Table 7 : Exceptions or error conditions that can arise during run-time

Exception Conditio n

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

Hardware Reset

RESET

00’0000h

00h

III

Software Reset

RESET

00’0000h

00h

III

Watchdog Timer Overflow

RESET

00’0000h

00h

III

Class A Hardware Traps:

Non-Maskable Interrupt

NMI

NMITRAP

00’0008h

02h

Stack Overflow

STKOF

STOTRAP

00’0010h

04h

Stack Underflow

STKUF

STUTRAP

00’0018h

06h

Class B Hardware Traps:

Undefined Opcode

UNDOPC

BTRAP

00’0028h

0Ah

Protected Instruction Fault

PRTFLT

BTRAP

00’0028h

0Ah

Illegal Word Operand Access

ILLOPA

BTRAP

00’0028h

0Ah

Illegal Instruction Access

ILLINA

BTRAP

00’0028h

0Ah

Illegal External Bus Access

ILLBUS

BTRAP

00’0028h

0Ah

Reserved

[2Ch –3Ch]

[0Bh – 0Fh]

Software Traps:

TRAP Instruction

Any

[00’0000h–

00’01FCh]

in steps of 4h

Any

[00h – 7Fh]

Current

CPU

Priority

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