ST10 datasheet(18/58 Pages) STMICROELECTRONICS

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ST10F163

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VIII - INTERRUPT SYSTEM

With an interrupt response time from 200 ns to

480ns (in the case of internal program execution),

the ST10F163 reacts quickly to the occurrence of

non-deterministic events.

The architecture of the ST10F163 supports sev-

eral mechanisms for fast and flexible response to

service requests that can be generated from vari-

ous sources internal or external to the microcon-

troller. Any of these interrupt requests can be

programmed to being serviced by the Interrupt

Controller or by the Peripheral Event Controller

(PEC). In a standard interrupt service, program

execution is suspended and a branch to the inter-

rupt vector table is performed. For a PEC service,

just one cycle is ‘stolen’ from the current CPU

activity. A PEC service is a single byte or word

data transfer between any two memory locations

with an additional increment of either the PEC

source or the destination pointer. An individual

PEC transfer counter is decremented for each

PEC service, except for the continuous transfer

mode. When this counter reaches zero, a stan-

dard interrupt is performed to the corresponding

source related vector location. PEC services are

suited to, for example, the transmission or recep-

tion of blocks of data. The ST10F163 has 8 PEC

channels,

each

which

offers

fast

inter-

rupt-driven data transfer capabilities.

A separate control register which contains an

interrupt request flag, an interrupt enable flag and

an interrupt priority bitfield, exists for each of the

possible interrupt sources. Via its related register,

each source can be programmed to one of sixteen

interrupt

priority

levels.

Once

having

been

accepted by the CPU, an interrupt service can

only be interrupted by a higher prioritized service

request. For the standard interrupt processing,

each of the possible interrupt sources has a dedi-

cated vector location.

Fast external interrupt inputs are provided to ser-

vice

external

interrupts

with

high

precision

requirements. These fast interrupt inputs, feature

programmable edge detection (rising edge, falling

edge or both edges).

Software interrupts are supported by means of the

‘TRAP’ instruction in combination with an individ-

ual trap (interrupt) number.

Table 6 shows all of the possible ST10F163 inter-

rupt

sources

and

the

corresponding

hard-

ware-related

interrupt

flags,

vectors,

vector

locations and trap (interrupt) numbers:

Table 6 : List of possible interrupt sources, flags, vector and trap numbers

Source of Interrupt or PEC

Service Request

Request

Flag

Enable

Flag

Interrupt

Vector

Location

Trap

Number

External Interrupt 0

CC8IR

CC8IE

CC8INT

00’0060h

18h

External Interrupt 1

CC9IR

CC9IE

CC9INT

00’0064h

19h

External Interrupt 2

CC10IR

CC10IE

CC10INT

00’0068h

1Ah

External Interrupt 3

CC11IR

CC11IE

CC11INT

00’006Ch

1Bh

External Interrupt 4

CC12IR

CC12IE

CC12INT

00’0070h

1Ch

External Interrupt 5

CC13IR

CC13IE

CC13INT

00’0074h

1Dh

External Interrupt 6

CC14IR

CC14IE

CC14INT

00’0078h

1Eh

External Interrupt 7

CC15IR

CC15IE

CC15INT

00’007Ch

1Fh

GPT1 Timer 2

T2IR

T2IE

T2INT

00’0088h

22h

GPT1 Timer 3

T3IR

T3IE

T3INT

00’008Ch

23h

GPT1 Timer 4

T4IR

T4IE

T4INT

00’0090h

24h

GPT2 Timer 5

T5IR

T5IE

T5INT

00’0094h

25h

GPT2 Timer 6

T6IR

T6IE

T6INT

00’0098h

26h

GPT2 CAPREL Register

CRIR

CRIE

CRINT

00’009Ch

27h

ASC0 Transmit

S0TIR

S0TIE

S0TINT

00’00A8h

2Ah

ASC0 Transmit Buffer

S0TBIR

S0TBIE

S0TBINT

00’011Ch

47h

ASC0 Receive

S0RIR

S0RIE

S0RINT

00’00ACh

2Bh

ASC0 Error

S0EIR

S0EIE

S0EINT

00’00B0h

2Ch

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