ST10 datasheet(10/58 Pages) STMICROELECTRONICS

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ST10F163

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IV - MEMORY ORGANIZATION

The memory space of the ST10F163 is configured

in a Von-Neumann architecture. Code memory,

data memory, registers and I/O ports are orga-

nized within the same linear address space which

includes 16 MBytes. The entire memory space

can be accessed bytewise or wordwise. Particular

portions of the on-chip memory have additionally

been made directly bit addressable.

1 KByte of on-chip RAM is provided as a storage

for user defined variables, for the system stack,

general purpose register banks and even for code.

A register bank can consist of up to 16 wordwide

(R0 to R15) and/or bytewide (RL0, RH0,

…, RL7,

RH7) General Purpose Registers (GPRs).

1024 bytes (2 * 512 bytes) of the address space

are reserved for the Special Function Register

areas (SFR space and ESFR space). SFRs are

wordwide registers which are used for controlling

and monitoring functions of the different on-chip

units. Unused SFR addresses are reserved for

other/future members of the ST10 family.

In order to meet the needs of system designs

where more memory is required than is provided

on chip, up to 16 MBytes of external RAM and/or

ROM can be connected to the microcontroller.

V - FLASH MEMORY

The ST10F163 provides 128KBytes of on-chip,

electrically erasable and re-programmable Flash

EPROM. The flash memory is organized in 32 bit

wide blocks. This allows double word instructions

to be fetched in one machine cycle. The flash

memory can be used for both code and data stor-

age. The flash memory is organized into four

banks of sizes 8K, 24K, 48K and 48Kbytes (table

2). Each of these banks can be erased indepen-

dently. This prevents unnecessary erasing of the

whole flash memory when only a partial erasing is

required (see Table 2).

Typical timing characteristics give 80

µs for word or

double word programming and 800 ms for block

erasing, at 25mhz system clock. the flash memory

has a typical endurance of 1000 erasing/program-

ming cycles. the flash memory can be pro-

grammed, either in a programming board, or in the

target system. the code to program or erase the

flash memory is executed from an external mem-

ory or from the on-chip ram, but not from the flash

memory itself. as a flexible and cost-saving alter-

native, the on-chip bootstrap loader may be used

to load and start the programming code.

the following considerations must be taken into

account for programming or erasing ‘on-line’ in the

target system:

– While operations are in progress, the flash mem-

ory can not be accessed as usual, no branch

can be made to the flash memory and no data

reads can be taken from the flash memory.

– If the two first blocks (8KB + 24KB) of the flash

memory are mapped to segment 0, no interrupt

or hardware trap must occur during program-

ming or erasing, as this would require a ‘forbid-

den’ branch to the flash memory.

A flash memory protection option, when activated,

prevents view access to the contents of the ROM

and the on-chip RAM, code operation from within

the flash memory continues as normal. During the

initialization phase, the first two blocks of the flash

memory (8KB + 24KB) can be mapped to seg-

ment 0 (addresses 00000h to 07FFFh), or to seg-

ment 1 (addresses 10000h to 17FFFh). This

makes it possible to use external memory for addi-

tional system flexibility.

Table 2 : FLASH memory bank organisation

Bank

Addresses (Segment 0)

Addresses (Segment 1)

Size (bytes)

000000h to 001FFFh

002000h to 007FFFh

018000h to 023FFFh

024000h to 02FFFFh

010000h to 011FFFh

012000h to 017FFFh

018000h to 023FFFh

024000h to 02FFFFh

24K

48K

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