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ST10 数据表(PDF) 37 Page - STMicroelectronics |
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ST10 数据表(HTML) 37 Page - STMicroelectronics |
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37 / 58 page ![]() ST10F163 37/58 XVI.4.9 - External clock drive XTAL1 VDD =5 V ± 10% VSS =0 V TA = 0 to +70 °C Parameter Symbol fCPU =fXTAL fCPU =fXTAL /2 fCPU =fXTAL *N N = 1.5/2,/2.5/3/4/5 Unit min max min max min max Oscillator period tOSC SR 401) 1000 20 500 40 * N 100 * N ns High time t1 SR 182) – 62) – 102) –ns Low time t2 SR 182) – 62) – 102) –ns Rise time t3 SR – 102) – 63) – 102) ns Fall time t4 SR – 102) – 62) – 102) ns 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 2. The input clock signal must reach the defined levels VIL and VIH2. Figure 13 : External clock drive XTAL1 t1 t3 t4 VIL t2 tOSC VIH2 |
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