ST10 datasheet(38/58 Pages) STMICROELECTRONICS

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ST10F163

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XVI.4.10 - Multiplexed bus

VDD =5 V ± 10%

VSS =0 V

TA = 0 to +70°CCL = 100 pF

ALE cycle time = 6 TCL + 2tA +tC +tF (120 ns at 25-MHz CPU clock without waitstates)

Table 16 : Multiplexed bus characteristics

Parameter

Symbol

Max. CPU Clock

25 MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

min.

max.

min.

max.

ALE high time

10 + tA

–

TCL - 10

+tA

–ns

Address setup to ALE

4 + tA

–

TCL -

16+ tA

–ns

Address hold after ALE

10 + tA

–

TCL - 10

+tA

–ns

ALE falling edge to RD, WR (with RW-delay)

10 + tA

–

TCL - 10

+tA

–ns

ALE falling edge to RD, WR (no RW-delay)

-10 + tA

–

-10 + tA

–ns

Address float after RD, WR (with RW-delay)

t10

–6–6

Address float after RD, WR (no RW-delay)

t11

–

TCL + 6

RD, WR low time (with RW-delay)

t12

30 + tC

–

2TCL - 10

+tC

–ns

RD, WR low time (no RW-delay)

t13

50 + tC

–

3TCL - 10

+tC

–ns

RD to valid data in (with RW-delay)

t14

–

20 + tC

–

2TCL - 20

+tC

RD to valid data in (no RW-delay)

t15

–

40 + tC

–

3TCL - 20

+tC

ALE low to valid data in

t16

–

+tA +tC

–

3TCL - 20

+tA +tC

Address/Unlatched CS to valid data in

t17

–

50 +2tA +

–

4TCL - 30

+2tA +tC

Data hold after RD rising edge

t18

0–0–

Data float after RD

t19

–

26 + tF

–

2TCL - 14

+tF

Data valid to WR

t22

20 + tC

–

2TCL - 20

+tC

–ns

Data hold after WR

t23

26 + tF

–

2TCL - 14

+tF

–ns

ALE rising edge after RD, WR

t25

26 + tF

–

2TCL - 14

+tF

–ns

Address/Unlatched CS hold after RD, WR

t27

26 + tF

–

2TCL - 14

+tF

–ns

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