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ST10F163

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XVI.4.12 - CLKOUT and READY

VDD =5 V ± 10%

VSS =0 V

TA = 0 to +70 °CCL = 100 pF

Table 18 : CLKOUT and READY characteristics

Parameter

Symbol

Max. CPU Clock

= 25MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

min.

max.

min.

max.

CLKOUT cycle time

t29

2TCL

CLKOUT high time

t30

–

TCL – 6

–

CLKOUT low time

t31

–

TCL – 10

–

CLKOUT rise time

t32

–4–4

CLKOUT fall time

t33

–4–4

CLKOUT rising edge to ALE falling edge

t34

0 + tA

10 + tA

0+ tA

10 + tA

Synchronous READY setup time to CLKOUT

t35

–14–

Synchronous READY hold time after CLKOUT

t36

4–4–

Asynchronous READY low time

t37

–

2TCL +

–ns

Asynchronous READY setup time

t58

–14–

Asynchronous READY hold time

t59

4–4–

Async. READY hold time after RD, WR high

(Demultiplexed Bus)

t60

0 + 2tA +

tC +tF

TCL - 20

+2tA +tC

+tF

1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds

even more time for deactivating READY.

The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle

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