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ST10 数据表(PDF) 52 Page - STMicroelectronics

部件名 ST10
功能描述  16-BIT MCU WITH 128KBYTE FLASH MEMORY
PDF  58 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10 数据表(HTML) 52 Page - STMicroelectronics

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ST10F163
52/58
XVI.4.13 - External bus arbitration
1. The ST10F163 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to get active.
3. The CS outputs will be resistive high (pullup) after
t
64.
VDD =5 V ± 10%
VSS =0 V
TA = 0 to +70 °C
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
Parameter
Symbol
Max. CPU Clock
= 25MHz
Variable CPU Clock
1/2TCL = 1 to 25MHz
min.
max.
min.
max.
HOLD input setup time to CLKOUT
t61
SR
20
–20–
ns
CLKOUT to HLDA high or BREQ low delay
t62
CC
–20–20
ns
CLKOUT to HLDA low or BREQ high delay
t63
CC
–20–20
ns
CSx release
t64
CC
–20–20
ns
CSx drive
t65
CC
-4
24
-4
24
ns
Other signals release
t66
CC
–20–20
ns
Other signals drive
t67
CC
-4
24
-4
24
ns
Figure 23 : External bus arbitration, releasing the bus
CLKOUT
HOLD
t61
HLDA
t63
Other
Signals
t66
1)
CSx
(On P6.x)
t64
1)
2)
BREQ
t62
3)



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