ST10 datasheet(11/58 Pages) STMICROELECTRONICS

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ST10F163

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V.1 - Programming/erasing with ST Embedded

Algorithm Kernel

In order to secure flash programming and erasing

operations, and also to simplify the software

development for programming and erasing the

Flash, the ST10F163 Flash is programmed or

erased by executing a specific sequence of

instructions (called ‘Unlock Sequence’) with com-

mand and parameters loaded into GPRs. The

Unlock Sequence’ invokes embedded kernel rou-

tines that checks the validity of the parameters

provided by the user, and decodes the command

(programming or erasing) and executes it.

When performing a programming command, the

Embedded Algorithm Kernel automatically times

the program pulse widths (taking in account the

CPU period provided as a parameter by the user)

and verifies proper cell programming.

When performing an erasing command, the

Embedded

Algorithm

Kernel

automatically

pre-programs the bank to be erased if it is not

already programmed. During erase, the Embed-

ded Algorithm Kernel automatically times the

erase pulse widths (taking in account the CPU

period provided as a parameter by the user) and

verifies proper cell erasing.

To start a program/erase operation, the user’s

application must perform an ‘Unlock Sequence’ to

trigger the flash ST Embedded Algorithms Kernel

(STEAK). Before using STEAK, proper parame-

ters must be assigned through the R0-R4 regis-

ters. The R0 register is the command register. The

other registers handle the address and data to be

programmed or sector to be erased. Table 3

defines the command sequence. A definition of

the codes used in Table 3 is given in Table 4.

Note

The read status for registers R1 to R3 is not used except for the return values, refer to “Return values” on page 13

Table 3 : Command -parameters definition

COMMAND

Single word programming

55Ash

AddOff

2TCL

Double Word programming

DD4sh

AddOff

DWL

DWH

2TCL

Block programming

AA5sh

BegAddOff

EndAddOff

SourceAddr

2TCL

Sector Erasing

EEEEh

5555h

Bnk

2TCL

Read Status

7777h

2TCL

Table 4 : Code definition

Abbreviation

Definition

Segment of the target flash memory cell

AddOff

Segment Offset of the target flash memory cell which must be even an value (word-aligned address).

Data (word) to be written in flash.

DWL,DWH

Data (double word, DHL = low word, DWH = high word to be written in Flash,

BegAddOff

Segment Offset of the FIRST target flash memory word to be written in a multiple programming com-

mand. This value must be even (word-aligned address)

EndAddOff

Segment Offset of the LAST Target Flash Memory word to be written in a Multiple programming

command.

Must be even value (word-aligned address). The value D = (EndAddOff - BegAddOff) must be: 0 <=

D < 16384 (ie. up to one page (16 KBytes) can be written in the flash with one multi-word program-

ming command).

SourceAdd

Start address for the source data (block) to be programmed. This address uses implicitly the data

paging mechanism of the CPU. SourceAdd value must respect the rules:

- SourceAdd + (EndAddOff - BegAddOff) < 16384.

- Page 0 and 1 can NOT be used for source data if SYSCON bit ROMS1 = ‘1’

Note: source data can be located in flash (In pages 0, 1, 6, 7, 8, 9, 10 or 11 if bit ROMS1 = ‘0’, or in

pages 4, 5, 6, 7, 8, 9, 10 or 11 if bit ROMS1 = ‘1’.

Bnk

Number of the Bank to be erased. Note that for security, R2 and R3 must hold the same value.

2TCL

CPU clock period in nseconds (e.g. R4 = 40d means CPU frequency is 25MHz).

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