ST10 datasheet(17/58 Pages) STMICROELECTRONICS

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ST10F163

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VII - CENTRAL PROCESSING UNIT (CPU)

The main core of the CPU consists of a 4-stage

instruction pipeline, a 16-bit arithmetic and logic

unit (ALU) and dedicated SFRs. Additional hard-

ware has been added for a separate multiply and

divide unit, a bit-mask generator and a barrel

shifter.

Based on these hardware provisions, most of the

ST10F163’s instructions can be executed in one

machine cycle. This requires 80ns at 25MHz CPU

clock. For example, shift and rotate instructions

are always processed in one machine cycle inde-

pendent of the number of bits to be shifted. All

multiple-cycle instructions have been optimized

for speed: branches in 2 cycles, a 16 x 16 bit mul-

tiplication in 5 cycles and a 32-/16 bit division in

10 cycles. The ‘Jump Cache’ pipeline optimiza-

tion, reduces the execution time of repeatedly per-

formed jumps in a loop, from 2 cycles to 1 cycle.

The CPU includes an actual register context. This

consists of up to 16 wordwide GPRs physically

allocated in the on-chip RAM area. A Context

Pointer

(CP)

determines

the

base

address of the active register bank to be accessed

by the CPU. The number of register banks is only

restricted by the available internal RAM space.

For easy parameter passing, one register bank

may overlap others.

A system stack of up to 1024 bytes is provided as

a storage for temporary data. The system stack is

allocated in the on-chip RAM area, and it is

accessed by the CPU via the stack pointer (SP)

Two

separate

SFRs,

STKOV

and

STKUN, are implicitly compared against the stack

pointer value upon each stack access for the

detection of a stack overflow or underflow.

The basic instruction length is either 2 or 4 bytes.

Possible operand types are bits, bytes and words.

A variety of direct, indirect or immediate address-

ing modes exist.

Figure 5 : CPU block diagram

ROM

Internal

RAM

1KByte

R15

General

Purpose

Registers

R15

MDH

MLD

Barrel-Shift

Mul./Div.-HW

Bit-Mask Gen.

ALU

16-Bit

Context Ptr

STKOV

STKUN

Exec. Unit

Instr. Ptr

Instr. Reg

4-Stage

Pipeline

PSW

SYSCON

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

Data Pg. Ptrs

Code Seg. Ptr.

CPU

128KBytes

FLASH

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