ST10F163

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The transition of shift and latch edge of SSPCLK is programmable. This figure uses the falling edge as shift edge (drawn bold).

The bit timing is repeated for all bits to be transmitted or received.

The active level of the chip enable lines is programmable. This figure uses an active low CE (drawn bold).

At the end of a transmission or reception the CE signal is disabled in single transfer mode. In continuous transfer mode it remains active.

Figure 26 : SSP read timing

SSPCLK

SSPCEx

SSPDAT

t

209

t

206

last Wr. Bit

Lst.In Bit

1)

3)

2)

1st.In Bit

t

210