ST10 datasheet(54/58 Pages) STMICROELECTRONICS

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ST10F163

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XVI.4.14 - Synchronous serial port timing

VCC =5 V ± 10%

VSS =0 V

TA = 0 to +70 °C

CL = 100 pF

Table 19 : Synchronous serial port timing characteristics

Parameter

Symbol

Max. Baudrate

= 12.5 / 10 MBd

Variable Baudrate

= 0.5 to 12.5 MBd

min.

max.

min.

max.

SSP clock cycle time

t200

80 / 100

80 /100

4 TCL

512 TCL

SSP clock high time

t201

30 / 40

– / –

t200/2 - 10

–

SSP clock low time

t202

30 / 40

– / –

t200/2 - 10

–

SSP clock rise time

t203

– / –

6 / 6

–

SSP clock fall time

t204

– / –

6 / 6

–

CE active before shift edge

t205

30 / 40

– / –

t200/2 - 10

–

CE inactive after latch edge

t206

70 / 90

90 / 110

t200 -10

t200 +10

Write data valid after shift edge

t207

– / –

10 / 10

–

Write data hold after shift edge

t208

0 / 0

– / –

–

Write data hold after latch edge

t209

34 / 44

46 / 56

t200/2 - 6

t200/2 + 6

Read data active after latch edge

t210

50 / 60

– / –

t200/2 + 10

–

Read data setup time before latch edge

t211

20 / 20

– / –

–

Read data hold time after latch edge

t212

0 / 0

– / –

–

Figure 25 : SSP write timing

204

203

SSPCLK

SSPCEx

SSPDAT

205

207

208

209

206

1st Bit

Last Bit

2nd Bit

200

201

202

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