ST10 datasheet(25/58 Pages) STMICROELECTRONICS

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ST10F163

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XII - WATCHDOG TIMER

The Watchdog Timer is a fail-safe mechanism

which the maximum malfunction time of the con-

troller

The Watchdog Timer is always enabled after a

reset of the chip, and can only be disabled in the

time interval until the EINIT (end of initialization)

instruction has been executed. In this way the

chip’s start-up procedure is always monitored.

The software must be designed to service the

Watchdog Timer before it overflows. If, due to

hardware or software related failures, the software

fails to do so, the Watchdog Timer overflows and

generates an internal hardware reset and pulls

the RSTOUT pin low in order to allow external

hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked

with the system clock divided either by 2 or by

128. The high byte of the Watchdog Timer register

can be set to a pre-specified reload value (stored

in WDTREL) in order to allow further variation of

the monitored time interval. Each time it is ser-

viced by the application software, the high byte of

the Watchdog Timer is reloaded. The Table 12

shows the watchdog time range which for a

25MHz CPU clock. Some numbers are rounded to

3 significant digits.

XIII - OSCILLATOR WATCHDOG (OWD)

The Oscillator Watchdog (OWD) monitors the

clock signal generated by the on-chip oscillator

(either with a crystal or via external clock drive).

For this operation the PLL provides a clock signal

to supervise transitions on the oscillator clock.

This PLL clock is independent from the XTAL1

clock. When the expected oscillator clock transi-

tions are missing, the OWD activates the PLL

Unlock/OWD interrupt node and supplies the CPU

with the PLL clock signal. Under these circum-

stances the PLL will oscillate with its basic fre-

quency.

A low level on pin OWE disables the OWD’s inter-

rupt output, so that the clock signal is derived from

the oscillator clock. The CPU clock source is only

switched back to the oscillator clock after a hard-

ware reset.

When the direct-drive, or direct-drive-with- pres-

caler clock option is selected, an oscillator watch-

dog is implemented. This provides a fail-safe

mechanism in the case of a loss of external clock.

After reset, the Oscillator Watchdog is enabled by

default. To disable the OWD, the bit OWDDIS (bit

4 of SYSCON register) must be set. When the

OWD is enabled, PLL runs on free-running fre-

quency, and increments the Oscillator Watchdog

counter. On each transition of XTAL1 pin, the

Oscillator Watchdog is cleared. If an external

clock failure occurs, then the Oscillator Watchdog

counter overflows (after 16 PLL clock cycles). The

CPU clock signal is switched to the PLL free-run-

ning clock signal, and the Oscillator Watchdog

Interrupt Request (XP3INT) is flagged. The CPU

clock will not switch back to the external clock

even if a valid external clock exits on XTAL1 pin.

Only a hardware reset can switch the CPU clock

source back to direct clock input.

When the OWD is disabled, the CPU clock is

always fed from the oscillator input and the PLL is

switched off to decrease power supply current.

Note

For security, rewrite WDTCON each time before the watchdog timer is serviced.

Table 12 : Watchdog time range for 25MHz CPU clock

Reload value

in WDTREL

Prescaler for fCPU

2 (WDTIN = ‘0’)

128 (WDTIN = ‘1’)

FFH

20.48

µs

1.31 ms

00H

5.24 ms

336 ms

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