ST10 datasheet(44/58 Pages) STMICROELECTRONICS

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ST10F163

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XVI.4.11 - Demultiplexed bus

VDD =5 V ± 10%

VSS =0 V

TA = 0 to +70 °CCL = 100 pF

ALE cycle time = 4 TCL + 2tA +tC +tF (80 ns at 25 MHz CPU clock without waitstates)

Table 17 : Demultiplexed bus characteristics

Parameter

Symbol

Max. CPU Clock

= 25MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

min.

max.

min.

max.

ALE high time

10 + tA

–

TCL -

10+ tA

–ns

Address setup to ALE

4 + tA

–

TCL -

16+ tA

–ns

Address/Unlatched CS setup to RD, WR

(with RW-delay)

t80

30 + 2tA

–

2TCL - 10

+2tA

–ns

Address/Unlatched CS setup to RD, WR

(no RW-delay)

t81

10 + 2tA

–

TCL -10

+2tA

–ns

RD, WR low time (with RW-delay)

t12

30 + tC

–

2TCL - 10

+tC

–ns

RD, WR low time (no RW-delay)

t13

50 + tC

–

3TCL - 10

+tC

–ns

RD to valid data in (with RW-delay)

t14

–

20 + tC

–

2TCL - 20

+tC

RD to valid data in (no RW-delay)

t15

–

40 + tC

–

3TCL - 20

+tC

ALE low to valid data in

t16

–

40 + tA +

–

3TCL - 20

+tA +tC

Address/Unlatched CS to valid data in

t17

–

50 + 2tA +

–

4TCL - 30

+2tA +tC

Data hold after RD rising edge

t18

0–0–

Data float after RD rising edge (with RW-delay1))

t20

–

26 + tF

–

2TCL - 14

+tF +

2tA

Data float after RD rising edge (no RW-delay1))

t21

–

10 + tF

–

TCL - 10

+tF +

2tA

Data valid to WR

t22

20 + tC

–

2TCL- 20

+tC

–ns

Data hold after WR

t24

10 + tF

–

TCL -

10+ tF

–ns

ALE rising edge after RD, WR

t26

-10 + tF

–-10 + tF

–ns

Address/Unlatched CS hold after RD, WR 2)

t28

0 + tF

–0 + tF

–ns

ALE falling edge to Latched CS

t38

-4 - tA

10 - tA

-4 - tA

10 - tA

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