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XVI.4.2 - Definition of internal timing

The internal operation of the ST10F163 is con-

of the CPU clock can trigger internal (e.g. pipe-

line) or external (e.g. bus cycles) operations.

The specification of the external timing (AC Char-

acteristics)

therefore

depends

on

the

time

between two consecutive edges of the CPU clock,

called “TCL” (see figure below).

The CPU clock signal can be generated by differ-

ent mechanisms. The duration of TCLs and their

variation (and also the derived external timing)

depends on the used mechanism to generate

culating the timings for the ST10F163.

The example for PLL operation shown in the fig-

ure above refers to a PLL factor of 4. The mecha-

nism used to generate the CPU clock is selected

during reset by the logic levels on pins P0.15-13

(P0H.7-5).

XVI.4.3 - Clock generation modes

The table below associates the combinations of these three bits with the respective clock generation mode.

Figure 11 : Generation mechanisms for the CPU clock

P0.15-13

(P0H.7-5)

CPU Frequency

External Clock Input

1. The external clock input range refers to a CPU clock range of 1...25 MHz.

Notes

111

2.5 to 6.25 MHz

Default configuration

110

3.33 to 8.33 MHz

101

5 to 12.5 MHz

100

2 to 5 MHz

011

1 to 25 MHz

2. The maximum depends on the duty cycle of the external clock signal.

010

6.66 to 16.6 MHz

001

2 to 50 MHz

3. The maximum input frequency is 25 MHz when using an external crystal with the internal oscillator; providing that internal serial resistance

of the crystal is less than 40

Ω. However, higher frequency can be applied with an external clock source, but in this case, the input clock

000

4 to 10 MHz

TCLTCL

Phase locked loop operation

Direct Clock Drive

TCL

TCL

Prescaler Operation

TCLTCL