H8S2245 datasheet(36/818 Pages) RENESAS

36 / 818 page

Rev.3.00 Mar. 26, 2007 Page xxxvi of xlii

REJ09B0355-0300

9.5

Interrupts ........................................................................................................................... 341

9.5.1

Interrupt Sources and Priorities............................................................................ 341

9.5.2

DTC Activation.................................................................................................... 342

9.5.3

A/D Converter Activation.................................................................................... 342

9.6

Operation Timing.............................................................................................................. 343

9.6.1

Input/Output Timing ............................................................................................ 343

9.6.2

Interrupt Signal Timing ....................................................................................... 348

9.7

Usage Notes ...................................................................................................................... 352

Section 10 8-Bit Timers..................................................................................................... 363

10.1

Overview........................................................................................................................... 363

10.1.1 Features................................................................................................................ 363

10.1.2 Block Diagram..................................................................................................... 364

10.1.3 Pin Configuration................................................................................................. 365

10.1.4 Register Configuration......................................................................................... 365

10.2

Register Descriptions ........................................................................................................ 366

10.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 366

10.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 367

10.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ................................ 367

10.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) .................................................. 368

10.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 370

10.2.6 Module Stop Control Register (MSTPCR) .......................................................... 373

10.3

Operation .......................................................................................................................... 374

10.3.1 TCNT Incrementation Timing ............................................................................. 374

10.3.2 Compare Match Timing....................................................................................... 375

10.3.3 Timing of External RESET on TCNT ................................................................. 377

10.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 377

10.3.5 Operation with Cascaded Connection.................................................................. 378

10.4

Interrupt Sources............................................................................................................... 379

10.4.1 Interrupt Sources and DTC Activation ................................................................ 379

10.4.2 A/D Converter Activation.................................................................................... 379

10.5

Sample Application........................................................................................................... 380

10.6

Usage Notes ...................................................................................................................... 381

10.6.1 Setting Module Stop Mode .................................................................................. 381

10.6.2 Contention between TCNT Write and Clear........................................................ 381

10.6.3 Contention between TCNT Write and Increment ................................................ 382

10.6.4 Contention between TCOR Write and Compare Match ...................................... 383

10.6.5 Contention between Compare Matches A and B ................................................. 384

10.6.6 Switching of Internal Clocks and TCNT Operation............................................. 384

10.6.7 Interrupts and Module Stop Mode ....................................................................... 386

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