H8S2245 datasheet(15/818 Pages) RENESAS

15 / 818 page

Rev.3.00 Mar. 26, 2007 Page xv of xlii

REJ09B0355-0300

Item

Page Revision (See Manual for Details)

9.2.5 Timer Status

312

Bit 0

Input Capture/Output Compare Flag A (TGFA)

Description amended

[Clearing conditions]

• When DTC is activated by TGIA interrupt while DISEL bit of

MRB in DTC is 0 with the transfer counter not being 0.

• When 0 is written to TGFA after reading TGFA = 1

9.7 Usage Notes

352

Description added

Note that the kinds of operation and contention described below

occur during TPU operation.

Module Stop Mode Setting

TPU operation can be disabled or enabled using the module stop

control register. The initial setting is for TPU operation to be

halted. Register access is enabled by clearing module stop

mode. For details, refer to section 18, Power-Down Modes.

Input Clock Restrictions

The input clock pulse width must be ...

Figure 9.52 Contention

between Overflow and

Counter Clearing

360

Figure 9.52 amended

TGF flag

Prohibited

TCFV flag

Figure 9.53 Contention

between TCNT Write and

Overflow

361

Figure 9.53 amended

Write signal

Address

TCNT address

TCNT

TCNT write cycle

H'FFFF

Prohibited

TCNT write data

TCFV flag

10.2.2 Time Constant

Registers A0 and A1

(TCORA0, TCORA1)

367

Description amended

... Note, however, that comparison is disabled during the T2 state

of a TCORA write cycle. ...

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