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数据搜索系统，热门电子元器件搜索 |
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H8S2245 数据表(PDF) 65 Page - Renesas Technology Corp |
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H8S2245 数据表(HTML) 65 Page - Renesas Technology Corp |
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65 / 818 page  Section 2 CPU Rev.3.00 Mar. 26, 2007 Page 23 of 772 REJ09B0355-0300 Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2.2). The exception vector table differs depending on the microcontroller. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Power-on reset exception vector Manual reset exception vector Exception vector 1 Exception vector 2 Exception vector table (Reserved for system use) Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16- bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. |
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