H8S2245 datasheet(32/818 Pages) RENESAS

32 / 818 page

Rev.3.00 Mar. 26, 2007 Page xxxii of xlii

REJ09B0355-0300

Section 6 Bus Controller ................................................................................................... 131

6.1

Overview........................................................................................................................... 131

6.1.1

Features................................................................................................................ 131

6.1.2

Block Diagram..................................................................................................... 132

6.1.3

Pin Configuration................................................................................................. 133

6.1.4

6.2

Register Descriptions ........................................................................................................ 135

6.2.1

Bus Width Control Register (ABWCR)............................................................... 135

6.2.2

Access State Control Register (ASTCR) ............................................................. 136

6.2.3

Wait Control Registers H and L (WCRH, WCRL).............................................. 137

6.2.4

Bus Control Register H (BCRH) ......................................................................... 141

6.2.5

Bus Control Register L (BCRL) .......................................................................... 143

6.3

Overview of Bus Control .................................................................................................. 145

6.3.1

Area Partitioning.................................................................................................. 145

6.3.2

Bus Specifications................................................................................................ 146

6.3.3

Memory Interfaces ............................................................................................... 147

6.3.4

Advanced Mode................................................................................................... 148

6.3.5

Areas in Normal Mode ........................................................................................ 149

6.3.6

Chip Select Signals .............................................................................................. 150

6.4

Basic Timing ..................................................................................................................... 150

6.4.1

On-Chip Memory (ROM, RAM) Access Timing ................................................ 151

6.4.2

On-Chip Peripheral Module Access Timing........................................................ 152

6.4.3

External Address Space Access Timing .............................................................. 153

6.5

Basic Bus Interface ........................................................................................................... 153

6.5.1

Overview.............................................................................................................. 153

6.5.2

Data Size and Data Alignment............................................................................. 153

6.5.3

Valid Strobes........................................................................................................ 155

6.5.4

Basic Timing........................................................................................................ 156

6.5.5

Wait Control ........................................................................................................ 164

6.6

Burst ROM Interface......................................................................................................... 166

6.6.1

Overview.............................................................................................................. 166

6.6.2

Basic Timing........................................................................................................ 166

6.6.3

Wait Control ........................................................................................................ 168

6.7

Idle Cycle .......................................................................................................................... 169

6.7.1

Operation ............................................................................................................. 169

6.7.2

Pin States in Idle Cycle ........................................................................................ 172

6.8

Bus Release....................................................................................................................... 172

6.8.1

Overview.............................................................................................................. 172

6.8.2

Operation ............................................................................................................. 172

6.8.3

Pin States in External Bus Released State............................................................ 173

6.8.4

Transition Timing ................................................................................................ 174

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