H8S2245 datasheet(39/818 Pages) RENESAS

39 / 818 page

Rev.3.00 Mar. 26, 2007 Page xxxix of xlii

REJ09B0355-0300

14.3

Interface to Bus Master ..................................................................................................... 512

14.4

Operation........................................................................................................................... 513

14.4.1 Single Mode (SCAN = 0) .................................................................................... 513

14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 515

14.4.3 Input Sampling and A/D Conversion Time ......................................................... 517

14.4.4 External Trigger Input Timing ............................................................................. 518

14.5

Interrupts ........................................................................................................................... 519

14.6

Usage Notes ...................................................................................................................... 519

Section 15 RAM .................................................................................................................. 525

15.1

Overview........................................................................................................................... 525

15.1.1 Block Diagram ..................................................................................................... 526

15.1.2 Register Configuration......................................................................................... 526

15.2

Register Descriptions ........................................................................................................ 527

15.2.1 System Control Register (SYSCR) ...................................................................... 527

15.3

Operation........................................................................................................................... 527

Section 16 ROM .................................................................................................................. 529

16.1

Overview........................................................................................................................... 529

16.1.1 Block Diagram ..................................................................................................... 530

16.1.2 Register Configuration......................................................................................... 530

16.2

Register Descriptions ........................................................................................................ 531

16.2.1 Bus Control Register L (BCRL) .......................................................................... 531

16.3

Operation........................................................................................................................... 532

16.4

PROM Mode ..................................................................................................................... 533

16.4.1 PROM Mode Setting............................................................................................ 533

16.4.2 Socket Adapter and Memory Map ....................................................................... 533

16.5

Programming..................................................................................................................... 536

16.5.1 Overview.............................................................................................................. 536

16.5.2 Programming and Verification............................................................................. 536

16.5.3 Programming Precautions .................................................................................... 541

16.5.4 Reliability of Programmed Data .......................................................................... 542

Section 17 Clock Pulse Generator .................................................................................. 543

17.1

Overview........................................................................................................................... 543

17.1.1 Block Diagram ..................................................................................................... 543

17.1.2 Register Configuration......................................................................................... 544

17.2

Register Descriptions ........................................................................................................ 544

17.2.1 System Clock Control Register (SCKCR) ........................................................... 544

17.2.2 Low Power Control Register (LPWCR) .............................................................. 545

17.3

Oscillator........................................................................................................................... 546

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