H8S2245 datasheet(44/818 Pages) RENESAS

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Section 1 Overview

Rev.3.00 Mar. 26, 2007 Page 2 of 772

REJ09B0355-0300

Table 1.1

Overview

Item

Specification

CPU

• General-register machine

 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers

or eight 32-bit registers)

• High-speed operation suitable for realtime control

 Maximum clock rate: 20 MHz

 High-speed arithmetic operations (20-MHz operation)

8/16/32-bit register-register add/subtract: 50 ns

× 16-bit register-register multiply:

1000 ns

32 ÷ 16-bit register-register divide:

1000 ns

• Instruction set suitable for high-speed operation

 Sixty-five basic instructions

 8/16/32-bit move/arithmetic instructions

 Unsigned/signed multiply and divide instructions

 Powerful bit-manipulation instructions

• Two CPU operating modes

 Normal mode:

64-kbyte address space

 Advanced mode: 16-Mbyte address space

Bus controller

• Address space divided into 8 areas, with bus specifications settable

independently for each area

• Chip select output possible for each area

• Choice of 8-bit or 16-bit access space for each area (CS0 to CS3)

• 2-state or 3-state access space can be designated for each area

• Number of program wait states can be set for each area

• Burst ROM directly connectable

• External bus release function

Data transfer

controller (DTC)

• Can be activated by internal interrupt or software

• Multiple transfers or multiple types of transfer possible for one activation

source

• Transfer possible in repeat mode, block transfer mode, etc.

• Request can be sent to CPU for interrupt that activated DTC

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