H8S2245 datasheet(31/818 Pages) RENESAS

31 / 818 page

Rev.3.00 Mar. 26, 2007 Page xxxi of xlii

REJ09B0355-0300

4.2.4

Interrupts after Reset............................................................................................ 98

4.2.5

State of On-Chip Supporting Modules after Reset Release ................................. 98

4.3

Interrupts ........................................................................................................................... 99

4.4

Trap Instruction................................................................................................................. 100

4.5

Stack Status after Exception Handling.............................................................................. 101

4.6

Notes on Use of the Stack ................................................................................................. 102

Section 5 Interrupt Controller .......................................................................................... 103

5.1

Overview........................................................................................................................... 103

5.1.1

Features ................................................................................................................ 103

5.1.2

Block Diagram ..................................................................................................... 104

5.1.3

Pin Configuration................................................................................................. 105

5.1.4

5.2

Register Descriptions ........................................................................................................ 106

5.2.1

System Control Register (SYSCR) ...................................................................... 106

5.2.2

Interrupt Control Registers A to C (ICRA to ICRC)............................................ 107

5.2.3

IRQ Enable Register (IER) .................................................................................. 108

5.2.4

IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 108

5.2.5

IRQ Status Register (ISR).................................................................................... 109

5.3

Interrupt Sources ............................................................................................................... 111

5.3.1

External Interrupts ............................................................................................... 111

5.3.2

Internal Interrupts................................................................................................. 112

5.3.3

Interrupt Exception Handling Vector Table......................................................... 112

5.4

Interrupt Operation............................................................................................................ 116

5.4.1

Interrupt Control Modes and Interrupt Operation ................................................ 116

5.4.2

Interrupt Control Mode 0 ..................................................................................... 119

5.4.3

Interrupt Control Mode 1 ..................................................................................... 121

5.4.4

Interrupt Exception Handling Sequence .............................................................. 124

5.4.5

Interrupt Response Times .................................................................................... 125

5.5

Usage Notes ...................................................................................................................... 126

5.5.1

Contention between Interrupt Generation and Disabling..................................... 126

5.5.2

Instructions that Disable Interrupts ...................................................................... 127

5.5.3

Times when Interrupts Are Disabled ................................................................... 127

5.5.4

Interrupts during Execution of EEPMOV Instruction.......................................... 127

5.5.5

IRQ Interrupt........................................................................................................ 127

5.5.6

NMI Interrupt Usage Notes.................................................................................. 128

5.6

DTC Activation by Interrupt............................................................................................. 128

5.6.1

Overview.............................................................................................................. 128

5.6.2

Block Diagram ..................................................................................................... 129

5.6.3

Operation ............................................................................................................. 129

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