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H8S2245 数据表(PDF) 20 Page - Renesas Technology Corp

部件名 H8S2245
功能描述  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
PDF  818 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S2245 数据表(HTML) 20 Page - Renesas Technology Corp

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Rev.3.00 Mar. 26, 2007 Page xx of xlii
REJ09B0355-0300
Item
Page Revision (See Manual for Details)
12.4 SCI Interrupt
462
Note
* added
When TDRE flag in ... The TDRE flag is cleared to 0
automatically when data transfer is performed by the DTC*. The
DTC cannot be activated by ...
When RDRF flag in ... The RDRF flag is cleared to 0
automatically when data transfer is performed by the DTC*. The
DTC cannot be activated by an ERI interrupt request.
Note:
* The flag is not cleared when DISEL is 0 and the transfer
counter value is not 0.
12.5 Usage Notes
464
Description added
The following points should be noted when using the SCI.
Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop
control register. The initial setting is for SCI operation to be
halted. Register access is enabled by clearing module stop
mode. For details, see section 18, Power-Down Modes.
Relation between Writes to TDR and TDRE Flag
467
Restrictions Concerning DTC Updating
...
• When RDR is read by the DTC, be sure to set the activation
source to the relevant SCI reception data full interrupt (RXI).
• The flag is cleared only when DISEL in DTC is 0 with the
transfer counter not being 0. When DISEL is 1,or DISEL is 0 with
the transfer counter being 0, the flag should be cleared by CPU.
Note that transmitting, in particular, may not successfully be
executed unless the TDRE flag is cleared by CPU.
467
to
472
Description of "Operation in Case of Mode Transition" and
"Switching from SCK Pin Function to Port Pin Function" added
13.2.2 Serial Status
Register (SSR)
479
Bit 2 TEND description amended
[Clearing conditions]
• When 0 is written to ...
• When the DTC* is activated by a TXI interrupt and write data
to TDR
[Setting conditions] ...
• When TDRE = 1 and ERS = 0 (normal transmission) 12.5 etu
after transmission of 1-byte serial character when GM = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 11.0 etu
after transmission of 1-byte serial character when GM = 1



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