H8S2245 datasheet(14/818 Pages) RENESAS

14 / 818 page

Rev.3.00 Mar. 26, 2007 Page xiv of xlii

REJ09B0355-0300

Item

Page Revision (See Manual for Details)

8.13.2 Register

Configuration

278

Port G Data Direction Register (PGDDR)

Description amended

... an undefined value will be read. PGDDR cannot be modified.

This register is a write-only register, and cannot be written by bit

manipulation instruction. For details, see section 2.10.4, Access

Methods for Registers with Write-Only Bits. PGDDR is initialized

by a power-on reset ...

8.14 Handling of

Unused Pins

283

Section 8.14 added

9.2.1 Timer Control

294

Bits 4 and 3

Clock Edge 1 and 0 (CKEG1, CKEG0)

Note amended

Note: Internal clock edge selection is valid when the input clock

φ/4 or slower. If φ/1 is selected as the input clock, this setting is

ignored and count at falling edge of

φ is selected.

9.2.5 Timer Status

311

Bit 3

Input Capture/Output Compare Flag D (TGFD)

Description amended

[Clearing conditions]

• When DTC is activated by TGID interrupt while DISEL bit of

MRB in DTC is 0 with the transfer counter not being 0.

• When 0 is written to TGFD after reading TGFD = 1

Bit 2

Input Capture/Output Compare Flag C (TGFC)

Description amended

[Clearing conditions]

• When DTC is activated by TGIC interrupt while DISEL bit of

MRB in DTC is 0 with the transfer counter not being 0.

• When 0 is written to TGFC after reading TGFC = 1

312

Bit 1

Input Capture/Output Compare Flag B (TGFB)

Description amended

[Clearing conditions]

• When DTC is activated by TGIB interrupt while DISEL bit of

MRB in DTC is 0 with the transfer counter not being 0.

• When 0 is written to TGFB after reading TGFB = 1

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