H8SSLASH2218 datasheet(391/750 Pages) RENESAS

391 / 750 page

Section 10 Watchdog Timer (WDT)

Rev.6.00 Jun. 03, 2008 Page 343 of 698

REJ09B0074-0600

10.3

Operation

10.3.1

Watchdog Timer Mode

To use the WDT as a watchdog timer, set the WT/

IT bit in TCSR and the TME bit to 1.

TCNT does not overflow while the system is operating normally. Software must prevent TCNT

overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.

When the RSTE bit of the RSTCSR is set to 1, and if the TCNT overflows, an internal reset signal

for this LSI is issued. In this case, select power-on reset or manual reset* by setting the RSTS bit

of the RSTCSR to 0.

If a reset caused by a signal input to the

RES pin occurs at the same time as a reset caused by a

WDT overflow, the

RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The

internal reset signal is output for 518 states.

When the TCNT overflows in watchdog timer mode, the WOVF bit of the RSTCSR is set to 1. If

the RSTE bit of the RSTCSR has been set to 1, an internal reset signal for the entire LSI is

generated at TCNT overflow.

Note: *

Supported only by the H8S/2218 Group.

TCNT value

H'00

Time

H'FF

WT/

IT = 1

TME = 1

H'00 written

to TCNT

WT/

IT = 1

TME = 1

H'00 written

to TCNT

518 states (WDT0)

Internal reset signal*

WT/

IT:

TME:

Legend:

Overflow

WOVF = 1

Timer mode select bit

Timer enabl bit

Note: * With WDT0, the internal reset signal is generated only when the RSTE bit is set to 1.

Internal reset

generated

Figure 10.2 Operation in Watchdog Timer Mode

H8S/2218 数据表(PDF) 391 Page - Renesas Technology Corp

H8S/2218 数据表(HTML) 391 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载