数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

H8S/2218 数据表(PDF) 456 Page - Renesas Technology Corp

部件名 H8S/2218
功能描述  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  750 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S/2218 数据表(HTML) 456 Page - Renesas Technology Corp

Back Button H8S/2218 Datasheet HTML 452Page - Renesas Technology Corp H8S/2218 Datasheet HTML 453Page - Renesas Technology Corp H8S/2218 Datasheet HTML 454Page - Renesas Technology Corp H8S/2218 Datasheet HTML 455Page - Renesas Technology Corp H8S/2218 Datasheet HTML 456Page - Renesas Technology Corp H8S/2218 Datasheet HTML 457Page - Renesas Technology Corp H8S/2218 Datasheet HTML 458Page - Renesas Technology Corp H8S/2218 Datasheet HTML 459Page - Renesas Technology Corp H8S/2218 Datasheet HTML 460Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 456 / 750 page
background image
Section 12 Serial Communication Interface
Rev.6.00 Jun. 03, 2008 Page 408 of 698
REJ09B0074-0600
12.4.5
Data Transmission (Asynchronous Mode)
Figure 12.9 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI)
is generated. Continuous transmission is possible because the TXI interrupt routine writes next
transmit data to TDR before transmission of the current transmit data has been completed.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark
state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
TDRE
TEND
0
1 frame
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
1
1
Data
Start
bit
Parity
bit
Stop
bit
Start
bit
Data
Parity
bit
Stop
bit
TXI interrupt
request generated
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt service routine
TEI interrupt
request generated
Idle state
(mark state)
TXI interrupt
request generated
Figure 12.9 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Figure 12.10 shows a sample flowchart for transmission in asynchronous mode.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com