H8SSLASH2218 datasheet(469/750 Pages) RENESAS

469 / 750 page

Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 421 of 698

REJ09B0074-0600

12.6.3

Serial Data Transmission (Clocked Synchronous Mode)

Figure 12.19 shows an example of SCI operation for transmission in clocked synchronous mode.

In serial transmission, the SCI operates as described below.

1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has

been written to TDR, and transfers the data from TDR to TSR.

2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt

(TXI) is generated. Continuous transmission is possible because the TXI interrupt routine

writes the next transmit data to TDR before transmission of the current transmit data has been

completed.

3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode

has been specified, and synchronized with the input clock when use of an external clock has

been specified.

4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).

5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission

of the next frame is started.

6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the

output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request

is generated. The SCK pin is fixed high.

Figure 12.20 shows a sample flow chart for serial data transmission. Even if the TDRE flag is

cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.

Make sure that the receive error flags are cleared to 0 before starting transmission. Note that

clearing the RE bit to 0 does not clear the receive error flags.

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