H8SSLASH2218 datasheet(478/750 Pages) RENESAS

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Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 430 of 698

REJ09B0074-0600

12.7.5

Receive Data Sampling Timing and Reception Margin

In Smart Card interface mode an internal clock generated by the on-chip baud rate generator can

only be used as a transmission/reception clock. In this mode, the SCI operates on a basic clock

with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed to 16 times in normal

asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the

falling edge of the start bit using the basic clock, and performs internal synchronization. As shown

in figure 12.28, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse

of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the

following formula.

M = | (0.5 –

) – (L – 0.5) F –

(1+ F) |

× 100 [%]

| D – 0.5 |

Where

M: Reception margin (%)

N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)

D: Clock duty (D = 0 to 1.0)

L: Frame length (L = 10)

F: Absolute value of clock frequency deviation

Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin

formula is as follows.

M = (0.5 – 1/2

× 372) × 100%

= 49.866%

Internal

basic clock

372 clocks

186 clocks

Receive data

(RxD)

Synchronization

sampling timing

Data sampling

timing

185

371 0

371

185

Start bit

Figure 12.28 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Transfer Rate)

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