H8SSLASH2218 datasheet(490/750 Pages) RENESAS

490 / 750 page

Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 442 of 698

REJ09B0074-0600

12.10.3

Mark State and Break Detection (Asynchronous Mode Only)

When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are

determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send

a break during serial data transmission. To maintain the communication line at mark state until TE

is set to 1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an

I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set

PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is

initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is

output from the TxD pin.

12.10.4

Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if

the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting

transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared

to 0.

12.10.5

Restrictions on Use of DMAC

• When an external clock source is used as the serial clock, the transmit clock should not be

input until at least 5

φ clock cycles after TDR is updated by the DMAC. Misoperation may

occur if the transmit clock is input within 4

φ clocks after TDR is updated. (figure 12.38)

• When RDR is read by the DMAC, be sure to set the activation source to the relevant SCI

reception end interrupt (RXI).

LSB

Serial data

SCK

Note: When operating on an external clock, set t>4 clocks.

TDRE

Figure 12.38 Example of Clocked Synchronous Transmission by DMAC

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