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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2218 数据表(PDF) 629 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 629 Page - Renesas Technology Corp |
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629 / 750 page  Section 17 Flash Memory (F-ZTAT Version) Rev.6.00 Jun. 03, 2008 Page 581 of 698 REJ09B0074-0600 17.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 17.13 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register 1, 2 (EBR1, EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E1 bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately (y+z+ α+β) ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit is B'0. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is N. |
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