H8SSLASH2218 datasheet(107/750 Pages) RENESAS

107 / 750 page

Section 2 CPU

Rev.6.00 Jun. 03, 2008 Page 59 of 698

REJ09B0074-0600

2.7.3

A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)

specified by the register field of the instruction, and the sum gives the address of a memory

operand. A 16-bit displacement is sign-extended when added.

2.7.4

specifies an address register (ERn) which contains the address of a memory operand. After the

operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the

address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for

longword transfer instruction. For word or longword transfer instruction, the register value should

be even.

address register (ERn) specified by the register field in the instruction code, and the result becomes

the address of a memory operand. The result is also stored in the address register. The value

subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer

instruction. For word or longword transfer instruction, the register value should be even.

2.7.5

Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32

The instruction code contains the absolute address of a memory operand. The absolute address

may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long

(@aa:32). Table 2.12 indicates the accessible absolute address ranges.

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits

(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).

For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can

access the entire address space.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits

are all assumed to be 0 (H'00).

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