H8SSLASH2218 datasheet(129/750 Pages) RENESAS

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Section 4 Exception Handling

Rev.6.00 Jun. 03, 2008 Page 81 of 698

REJ09B0074-0600

Section 4 Exception Handling

4.1

Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or

interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur

simultaneously, they are accepted and processed in order of priority. Exception sources, the stack

structure, and operation of the CPU vary depending on the interrupt control mode. For details on

the interrupt control mode, refer to section 5, Interrupt Controller.

Table 4.1

Exception Types and Priority

Priority

Exception Type

Start of Exception Handling

High

Reset

Starts immediately after a low-to-high transition at the

RES or

MRES* pin, or when the watchdog timer overflows. The CPU

enters the reset state when the

RES pin is low. The CPU enters

the manual reset state when the

MRES pin* is low.

Trace

Starts when execution of the current instruction or exception

handling ends, if the trace (T) bit in the EXR is set to 1. This is

enabled only in trace interrupt control mode 2. Trace exception

processing is not performed after RTE instruction execution.

Interrupt

Starts when execution of the current instruction or exception

handling ends, if an interrupt request has been issued. Note that

after executing the ANDC, ORC, XORC, or LDC instruction or at

the completion of reset exception processing, no interrupt is

detected.

Low

Trap instruction

(TRAPA)

Started by execution of a trap instruction (TRAPA). Trap exception

processing is always accepted in program execution state.

Note:

Supported only by the H8S/2218 Group.

4.2

Exception Sources and Exception Vector Table

Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception

sources and their vector addresses. Since the usable modes differ depending on the product, for

details on each product, refer to section 3, MCU Operating Modes.

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