H8SSLASH2218 datasheet(132/750 Pages) RENESAS

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Section 4 Exception Handling

Rev.6.00 Jun. 03, 2008 Page 84 of 698

REJ09B0074-0600

Table 4.3

Reset Types

Reset Transition Condition

Internal State

Type

MRES

RES

CPU

On-Chip Peripheral Modules

Power-on reset

Low

Initialized

Manual reset

Low

High

Initialized

Initialized, except for bus

controller and I/O ports

Legend:

×: Don't care

A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a

manual reset.

When the

MRES pin* is used, MRES pin* input must be enabled by setting the MRESE bit to 1 in

SYSCR.

Note:* Supported only by the H8S/2218 Group.

4.3.2

Reset Exception Handling

When the

RES or MRES* pin goes low, this LSI enters the reset. To ensure that this LSI is reset,

hold the

RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the

RES or MRES* pin low for at least 20 states.

When the

RES or MRES* pin goes high after being held low for the necessary time, this LSI starts

reset exception handling as follows.

1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized,

the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.

2. The reset exception handling vector address is read and transferred to the PC, and program

execution starts from the address indicated by the PC.

Note: * Supported only by the H8S/2218 Group.

Figures 4.1 and 4.2 show examples of the reset sequence.

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