H8SSLASH2218 datasheet(158/750 Pages) RENESAS

158 / 750 page

Section 5 Interrupt Controller

Rev.6.00 Jun. 03, 2008 Page 110 of 698

REJ09B0074-0600

CPU

I, I2 to I0

DMAC

IRQ

interrupt

On-chip

peripheral

module

Interrupt source

clear signal

Interrupt

request

Disenable

signal

Clear

signal

Selection

circuit

CPU interrupt

request vector

number

Interrupt controller

Determination of

priority

Control logic

Figure 5.7 Interrupt Control for DMAC

Selection of Interrupt Source: An activation factor is directly input to each channel of the

DMAC. The activation factors for each channel of the DMAC are selected by the DTF3 to DTF0

bits of DMACR. The DTA bit of DMABCR can be used to select whether the selected activation

factors are managed by the DMAC. By setting the DTA bit to 1, the interrupt factor which was the

activation factor for that DMAC cannot act as the CPU interrupt factor.

Interrupt factors other than the interrupts managed by the DMAC is CPU interrupt request.

Determination of Priority: The activation source is directly input to each channel of DMAC.

Operation Order: If the same interrupt is selected as the DMAC activation factor or CPU

interrupt factor, these operate independently. They operate in accordance with the respective

operating states and bus priorities.

Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification

of the DTA bit of DMAC's DMABCR.

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