H8SSLASH2218 datasheet(156/750 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.6.00 Jun. 03, 2008 Page 108 of 698

REJ09B0074-0600

5.6.4

Interrupt Response Times

Table 5.4 shows interrupt response times

⎯ the interval between generation of an interrupt request

and execution of the first instruction in the interrupt handling routine. The execution status

symbols used in table 5.4 are explained in table 5.5.

This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip

ROM and the stack area in on-chip RAM, enabling high-speed processing.

Table 5.4

Interrupt Response Times

Normal Mode*

Advanced Mode

No.

Execution State

Interrupt

Control

Mode 0

Interrupt

Control

Mode 2

Interrupt

Control

Mode 0

Interrupt

Control

Mode 2

Interrupt priority determination*

Number of wait states until

executing instruction ends*

1 to 19+2·SI 1 to 19+2·SI 1 to 19+2·SI 1 to 19+2·SI

PC, CCR, EXR stack save

2·SK

3·SK

2·SK

3·SK

Vector fetch

2·SI

Instruction fetch*

2·SI

Internal processing*

Total (using on-chip memory)

11 to 31

12 to 32

13 to 33

Notes: 1. Two states in case of internal interrupt.

2. Refers to MULXS and DIVXS instructions.

3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.

4. Internal processing after interrupt acceptance and internal processing after vector fetch.

5. Not available in this LSI.

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