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H8S/2218 数据表(PDF) 152 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 152 Page - Renesas Technology Corp |
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152 / 750 page ![]() Section 5 Interrupt Controller Rev.6.00 Jun. 03, 2008 Page 104 of 698 REJ09B0074-0600 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution status Interrupt generated? NMI IRQ0 IRQ1 EXIRQ1 I = 0 Save PC and CCR I ←1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 |
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