H8SSLASH2218 datasheet(149/750 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.6.00 Jun. 03, 2008 Page 101 of 698

REJ09B0074-0600

5.5

Interrupt Exception Handling Vector Table

Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.

For default priorities, the lower the vector number, the higher the priority. Priorities among

modules can be set by means of the IPR. Modules set at the same priority will conform to their

default priorities. Priorities within a module are fixed.

Table 5.2

Interrupt Sources, Vector Addresses, and Interrupt Priorities

Vector Address*

Interrupt

Source

Origin of Interrupt

Source

Vector

Number

Advanced Mode

IPR

Priority

External pins

NMI

H'001C

High

IRQ0

H'0040

IPRA6 to IPRA4

IRQ1

H'0044

IPRA2 to IPRA0

IRQ2

H'0048

IPRB6 to IPRB4

IRQ3

H'004C

IRQ4

H'0050

IPRB2 to IPRB0

RTC

IRQ5

H'0054

USB

IRQ6

H'0058

IPRC6 to IPRC4

External pins

IRQ7

H'005C

Watchdog Timer WOVI

H'0064

IPRD6 to IPRD4

A/D

ADI

H'0070

IPRE2 to IPRE0

TGI0A

H'0080

TGI0B

H'0084

TGI0C

H'0088

TGI0D

H'008C

TPU channel 0

TGI0V

H'0090

IPRF6 to IPRF4

TPU channel 1

TGI1A

H'00A0

IPRF2 to IPRF0

TGI1B

H'00A4

TGI1V

H'00A8

TGI1U

H'00AC

Low

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