H8SSLASH2218 datasheet(146/750 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.6.00 Jun. 03, 2008 Page 98 of 698

REJ09B0074-0600

Bit

Bit Name

Initial Value

R/W

Description

IRQ0SCB

IRQ0SCA

R/W

IRQ0 Sense Control B

IRQ0 Sense Control A

00: Interrupt request generated at

IRQ0 input low level

01: Interrupt request generated at falling edge of

IRQ0

input

10: Interrupt request generated at rising edge of

IRQ0

input

11: Interrupt request generated at both falling and

rising edges of

IRQ0 input

Legend:

×: Don’t care

Notes: 1. IRQ6 is an interrupt only for the on-chip USB.

2. IRQ5 is an interrupt only for the on-chip RTC.

5.3.4

IRQ Status Register (ISR)

ISR indicates the status of IRQ7 to IRQ0 interrupt requests.

Bit

Bit Name

Initial Value R/W

Description

IRQ7F

R/(W)*

IRQ6F

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

IRQ0F

R/(W)*

[Setting condition]

When the interrupt source selected by the ISCR

registers occurs

[Clearing conditions]

• Cleared by reading IRQnF flag when IRQnF = 1,

then writing 0 to IRQnF flag

• When interrupt exception handling is executed

when low-level detection is set and ,

IRQn input is

high

• When IRQn interrupt exception handling is executed

when falling, rising, or both-edge detection is set

Note: * Only 0 can be written, to clear flags.

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