H8SSLASH2218 datasheet(144/750 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.6.00 Jun. 03, 2008 Page 96 of 698

REJ09B0074-0600

5.3.3

IRQ Sense Control Registers H and L (ISCRH, ISCRL)

The ISCR registers select the source that generates an interrupt request at pins

IRQ7 to IRQ0.

Bit

Bit Name

Initial Value

R/W

Description

IRQ7SCB

IRQ7SCA

R/W

IRQ7 Sense Control B

IRQ7 Sense Control A

00: Interrupt request generated at

IRQ7 input low level

01: Interrupt request generated at falling edge of

IRQ7

input

10: Interrupt request generated rising edge of

IRQ7

input

11: Interrupt request generated at both falling and

rising edges of

IRQ7 input

IRQ6SCB

IRQ6SCA

R/W

IRQ6*

1 Sense Control B

IRQ6*

1 Sense Control A

00: Setting prohibited when using on-chip USB

suspend or resume interrupt

01: Interrupt request generated at falling edge of

IRQ6

input

1x: Setting prohibited

IRQ5SCB

IRQ5SCA

R/W

IRQ5*

2 Sense Control B

IRQ5*

2 Sense Control A

00: Setting prohibited when using RTC interrupt

01: Interrupt request generated at falling edge of

IRQ5

input

1x: Setting prohibited

IRQ4SCB

IRQ4SCA

R/W

IRQ4 Sense Control B

IRQ4 Sense Control A

00: Interrupt request generated at

IRQ4 input low level

01: Interrupt request generated at falling edge of

IRQ4

input

10: Interrupt request generated at rising edge of

IRQ4

input

11: Interrupt request generated at both falling and

rising edges of

IRQ4 input

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