H8SSLASH2218 datasheet(142/750 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.6.00 Jun. 03, 2008 Page 94 of 698

REJ09B0074-0600

5.3.1

Interrupt Priority Registers A to G, J, K, M (IPRA to IPRG, IPRJ, IPRK, IPRM)

The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI.

The correspondence between interrupt sources and IPR settings is shown in section 5.5, Interrupt

Exception Handling Vector Table. Setting a value in the range from H'0 to H'7 in the 3-bit groups

of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.

Bit

Bit Name

Initial Value

R/W

Description

–

Reserved

This bit is always read as 0 and cannot be modified.

IPR6

IPR5

IPR4

R/W

These bits set the priority of the corresponding

interrupt source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

–

Reserved

This bit is always read as 0 and cannot be modified.

IPR2

IPR1

IPR0

R/W

These bits set the priority of the corresponding

interrupt source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

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