H8SSLASH2218 datasheet(197/750 Pages) RENESAS

197 / 750 page

Section 6 Bus Controller

Rev.6.00 Jun. 03, 2008 Page 149 of 698

REJ09B0074-0600

6.7.2

Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion using the

WAIT

pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.6.4, Wait

Control.

Wait states cannot be inserted in a burst cycle.

6.8

Idle Cycle

When the H8S/2218 Group accesses external space, it can insert a 1-state idle cycle (TI) between

bus cycles in the following two cases: (1) when read accesses between different areas occur

consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an

idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output

floating time, and high-speed memory, I/O interfaces, and so on.

Consecutive Reads between Different Areas: If consecutive reads between different areas occur

while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read

cycle.

Figure 6.22 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,

each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in

cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,

and a data collision is prevented.

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