H8SSLASH2218 datasheet(199/750 Pages) RENESAS

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Section 6 Bus Controller

Rev.6.00 Jun. 03, 2008 Page 151 of 698

REJ09B0074-0600

Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH

is set to 1, an idle cycle is inserted at the start of the write cycle.

Figure 6.23 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an

idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and

the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.

Address bus

φφ

Bus cycle A

Data bus

Bus cycle B

Long output floating time

Data collision

(a) Idle cycle not inserted

(ICIS0 = 0)

Address bus

Bus cycle A

Data bus

Bus cycle B

(b) Idle cycle inserted

(Initial value ICIS0 = 1)

CS (area A)

CS (area B)

HWR

CS (area A)

CS (area B)

Figure 6.23 Example of Idle Cycle Operation (2)

Relationship between Chip Select (

CS) Signal and Read (RD) Signal: Depending on the

system's load conditions, the

RD signal may lag behind the CS signal. An example is shown in

figure 6.24.

In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap

between the bus cycle A

RD signal and the bus cycle B CS signal.

Setting idle cycle insertion, as in (b), however, will prevent any overlap between the

RD and CS

signals.

In the initial state after reset release, idle cycle insertion (b) is set.

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